1. Field of the Invention
The present invention relates to a semiconductor memory testing apparatus suitable for testing a semiconductor memory such as a memory formed as an integrated circuit (a semiconductor integrated circuit memory, hereinafter referred to an IC memory), and more particularly, relates to a failure analysis memory for storing test results of an IC memory.
2. Description of the Related Art
FIG. 4 shows a basic construction of a conventional semiconductor memory testing apparatus of this type. The illustrated memory testing apparatus comprises a timing generator 11, a pattern generator (PTN GEN) 12, a waveform shaping device (WAVE SHAPE) 14, a logical comparator (LOGIC COMPA) 16, and a failure analysis memory (FAIL MEM) 13.
The pattern generator 12 generates, when a reference clock generated by the timing generator 11 is supplied thereto, an address signal (ADR), a data signal of a predetermined test pattern (DATA) and a control signal (CNTL) which are to be applied to an IC memory to be tested or under test (hereinafter, also referred to simply as memory under test or MUT) 15. These signals are supplied to the waveform shaping device 14 where they are shaped to waveforms required to test the memory 15, and thereafter the shaped waveforms are applied to the memory under test 15.
The memory under test 15 is controlled in its writing operation in which test pattern data signals (DATA) are written thereinto or its reading operation in which the written data signals are read out thereof by a control signal applied to the memory under test 15 through the waveform shaping device 14, and under the control of this control signal, test pattern data signals supplied from the waveform shaping device 14 are written into the memory under test 15 or the written test pattern data signals are read out thereof. The test pattern data signals written into the memory under test 15 are read out later which are, in turn, supplied to the logical comparator 16 where the read out signals are sequentially compared with expected value pattern data signals (EXP) supplied from the pattern generator 12 one by one, thereby to detect whether there is an anti-coincidenc e or a mismatch between the read out signal and the expected value pattern data signal. By these comparison results, a decision is rendered that the memory under test is a failure memory or a pass (conformable or good) memory.
When there is a mismatch between both signals, a failure signal (FAIL) is outputted from the logical comparator 16 to the failure analysis memory 13 in which a failure data corresponding to this failure signal is stored at an address of the failure analysis memory 13 specified by an address signal (ADR) from the pattern generator 12. In general, when the read out signal coincides with the expected value pattern data signal, the logical comparator 16 generates a pass signal, but a data corresponding to this pass signal is not stored in the failure analysis memory 13.
In such a way, failure data each representing a position of a failure memory cell of the memory under test 15, which have occurred during a sequence of tests, are stored in the failure analysis memory 13. After completion of the tests, a failure analysis of the memory under test 15 is performed with reference to the failure data stored in the failure analysis memory 13. For example, in case such failure data are utilized for relieving the failure memory cells, a failure map is created based on the read out failure data to determine whether the detected failure positions (failure memory cells) can be relieved by relieving means previously provided on the memory under test 15.
If the failure analysis memory 13 has four input/output terminals I/O1, I/O2, I/O3, and I/O4 (the bit width of the memory under test 15 is four bits), and hence a test pattern data signal of four bits is applied to the memory under test 15, the failure analysis memory 13 is arranged or constructed as shown in FIG. 5.
FIG. 5 shows in the block form concrete constructions of the failure analysis memory 13 and the logical comparator 16 shown in FIG. 4 together with the memory under test (MUT) 15. To the memory under test 15 are supplied an address signal and a test pattern data signal of four bits from the pattern generator 12 through waveform shaping device 14, thereby to perform writing of the test pattern data signal in the memory under test 15 and reading of the written test pattern data signal therefrom.
The test pattern data signal of four bits read out of the memory under test 15 is compared with an expected value pattern data signal given from the pattern generator 12 in the logical comparator 16. The logical comparator 16 comprises four logic gates connected to the corresponding input/output terminals I/O1-I/O4 of the memory under test 15 respectively, and outputs a pass signal of logic "1" (H (high) level) indicating that this memory cell is normal when the test pattern data signal read out of the memory under test 15 coincides with the expected value pattern data signal supplied from the pattern generator 12 and outputs a failure signal of logic "0" (L (low) level) indicating that this memory cell is abnormal or failure when both the signals do not coincide with each other. These failure signals FAL1-FAL4 are supplied to the failure analysis memory 13.
The failure analysis memory 13 is constituted, since the bit width of the memory under test 15 is four bits in this example, by four memories each having its data width of one bit connected to the corresponding input/output terminals I/O1-I/O4 of the memory under test 15 respectively, for example, four static RAMs (random access memory, hereinafter referred to as X1SRAM), and the failure data are stored in these four X1SRAMs (X1SRAM.sub.1, X1SRAM.sub.2, X1SRAM.sub.3, X1SRAM.sub.4).
In the illustrated example, since the failure signals FAL1-FAL4 outputted from the logical comparator 16 are supplied to chip select terminals /CS of the X1SRAM.sub.1, X1SRAM.sub.2, X1SRAM.sub.3 and X1SRAM.sub.4, respectively, an L-logic is inputted to the chip select terminal /CS of each of the X1SRAM.sub.1, X1SRAM.sub.2, X1SRAM.sub.3 and X1SRAM.sub.4 only when there is a mismatch between the test pattern data signal and the expected value pattern data signal, thereby to enable that X1SRAM to which the L-logic is inputted. As a result, in synchronism with a write-in command pulse /WE supplied to a write-in terminal /WE of each of the X1SRAM.sub.1, X1SRAM.sub.2, X1SRAM.sub.3 and X1SRAM.sub.4 , an H-logic supplied to data input terminals FD0-FD3 of the X1SRAM.sub.1, X1SRAM.sub.2, X1SRAM.sub.3 and X1SRAM.sub.4 is written in that X1SRAM at an address specified by an address signal applied to an address terminal An thereof at that time.
In such a manner, the failure data are sequentially written in each of the X1SRAM.sub.1, X1SRAM.sub.2, X1SRAM.sub.3 and X1SRAM.sub.4. FIG. 6 shows an example of the format of stored failure data in the failure analysis memory 13.
The above discussed construction and operation of the failure analysis memory 13 are ones which are used in the semiconductor memory testing apparatus in case of testing semiconductor memories operating at a normal rate or speed (relatively low rate). A construction or configuration for testing semiconductor memories operating at a high rate or speed is also added to the semiconductor memory testing apparatus.
Specifically, the construction added to the semiconductor memory testing apparatus is arranged such that a plurality of memories having the same storage capacity and operating at a normal rate are provided in the failure analysis memory 13 for each of the input/output terminals of the memory under test 15, and the plurality of the memories for each input/output terminal are accessed at different time points shifted bit by bit in time, that is, time divisionally operated, thereby to increase the operating rate of the failure analysis memory 13 as a whole so that it can store failure data read out from an IC memory operating at high rate. Such time divisional operation will be referred to as interleave operation hereinafter.
In order to effect the interleave operation, it is necessary in the case shown in FIG. 5 that the memory construction (the construction consisting of X1SRAM.sub.1 -X1SRAM.sub.4) of the failure analysis memory 13 shown in the drawing is provided by the number of time division (hereinafter referred to as the number of ways or phases of interleave). One memory construction is also called a bank, and if the number of ways of interleave is 4, then four banks are needed to be provided. That is, it is necessary to provide four sets of the memory construction consisting of X1SRAM.sub.1 -X1SRAM.sub.4. X1SRAM.sub.1 -X1SRAM.sub.4 of each of the four memory constructions are interleaved (time divisionally operated).
FIG. 7 is waveforms showing an outline of the interleave operation of four ways or phases. Failure data of high rate HFAL read out from a memory under test of high operating rate are distributed to and stored in four banks #1-#4 shown in FIG. 7C in accordance with bank select signals of four phases S1, S2, S3 and S4 shown in FIG. 7B, respectively. Accordingly, X1SRAM.sub.1 -X1SRAM.sub.4 constituting each of the four banks #1-#4 may operate at a period T which is four times as long as the period of the high rate failure data HFAL.
FIG. 8 shows one example of the construction of the conventional failure analysis memory 13 the operation mode of which can be switched to one of the high rate and the low rate so that it can operate in either one of the high rate mode and the low rate mode. In this example, a case is shown in which the failure analysis memory 13 is constituted by a plurality of failure analysis memory units 13.sub.1 -13.sub.m.
Assuming that the number of memories under test which can be tested concurrently by the memory testing apparatus is m without distinction of the high rate test mode and the low rate test mode, m failure analysis memory units 13.sub.1 -13.sub.m are provided, too. In addition, each of the m failure analysis memory units 13.sub.1 -13.sub.m has a memory control part MCON and a memory block MBLK provided therein. The memory block MBLK has banks (memory constructions) BNC#1-BNC#n the number of which is equal to that of ways of the interleave operation. In the illustrated example, each memory block has n banks BNC#1-BNC#n in order to make it possible that the interleave operation up to n ways can be effected. Each bank is constituted by a plurality of memories X1SRAMs the number of which is equal to the bit width of a memory under test.
The memory control part MCON comprises a failure format part FLFO, a bank selector part BLSE, an operating frequency register FRG, and a shifter SFT.
The failure format part FLFO cuts or takes out a bit width corresponding to the bit width outputted from the memory under test to supply to the respective banks BNC#1-BNC#n a failure data having the same bit width as the bit width outputted from the memory under test.
The bank selector part BLSE outputs a bank select signal corresponding to the high rate test mode or the low rate test mode. That is, in the low rate test mode, the bank selector part BLSE produces a bank select signal based on a value set in the operating frequency register FRG, and outputs, in accordance with an address signal (commonly a higher bit or bits of the address signal generated from the pattern generator 12 for selecting one of X1SRAMs), this bank select signal to, generally, only the first bank BNC#1 to set that bank BNC#1 in the operation mode.
In the high rate test mode, the shifter SFT operates and the bank selector part BLSE produces bank select signals of multi-phases (see FIG. 7B) the number of which corresponds to that of ways of the interleave operation. The bank select signals of multi-phases are sequentially supplied to the n banks BNC#1-BNC#n one signal for one bank in accordance with the higher bit or bits of the address signal, thereby to effect the interleave operation of the banks BNC#1-BNC#n.
To each of address input terminals An of plural (the number corresponding to the bit width of the memory under test, which is four (4) in this example) X1SRAMs constituting each of the banks BNC#1-BNC#n is supplied the same address signal (commonly a lower bit or bits of the address signal generated from the pattern generator 12) as that supplied to the memory under test 15, and the same address of each X1SRAM as that of the memory under test is accessed by the address signal. In addition, an H-logic is being applied to an data input terminal FD of each X1SRAM, and if a failure data of L-logic is supplied to the chip select terminal /CS (if the data read out of the memory under test 15 does not coincide with the expected value data), an H-logic is written at an address specified by an address signal supplied to the address terminal An at that time.
As described above, heretofore, the semiconductor memory testing apparatus has the construction by which the testing apparatus can operate in either one of the low rate test mode and the high rate test mode. In the low rate test mode, as shown in FIG. 9, the construction is arranged such that the first bank BNC#1 in each memory block MBLK is mainly used, and hence the remaining banks BNC#2-BNC#n in each memory block remain unused.
As a result, in the low rate test mode, the memories prepared in the failure analysis memory 13 are actually used only by a portion thereof, that is, only a memory capacity corresponding to the quotient of the total memory capacity divided by the number of ways of the interleave operation is actually used. Accordingly, the cost (test cost) required for testing IC memories becomes high. For example, in case the number of ways of the interleave operation is 4 as the illustrated example, only memories or memory capacity equal to 1/4 of the total memories or memory capacity prepared in the failure analysis memory 13 are actually used, and therefore, the ratio of the cost required for equipping the memory testing apparatus to the number of semiconductor memories that the testing apparatus can test within unit time is large, resulting in high test cost.
Generally, to reduce the cost required for testing semiconductor memories is attained by increasing the number of semiconductor memories that the testing apparatus can test at the same time. However, in practice, the more the number of semiconductor memories that the testing apparatus can test at the same time is increased, the more the amount of memories (memory capacity of the failure analysis memory) which remains unused in the low rate test mode is increased. As a result, the cost required for manufacturing a memory testing apparatus becomes high which results in a disadvantage that the test cost is increased.